The present invention relates to integrated circuit assembly and packaging, and more particularly to the mounting of leadless integrated circuit chip carriers upon a printed circuit board.
The most widely utilized integrated circuit package presently is the dual-in-line package where the electrical leads extend from the package in two aligned parallel arrays from opposed sides of the package. The electrical leads extend downward to permit insertion into and connection with printed circuit board mounting holes. These electrical leads are subject to distortion during handling and can create problems in automated assembly systems.
A more recent package for such integrated circuit chips is the leadless chip carrier, in which the IC chip is mounted on one side of an insulating chip carrier with generally planar electrical connections between the chip periphery leads and a conductor pattern on the carrier. The chip carrier carries the conductor pattern to the opposite side of the carrier, typically by way of a plurality of castellations formed in the perimeter of the chip carrier, and with the conductor pattern extending down along the castellations. The leadless chip carrier is then aligned over the mounting pads or conductor pattern on the printed circuit board and soldered thereto.
The present techniques for attaching the leadless carrier to the printed circuit board substrate and making electrical connection include the screening of solder paste on the substrate, placing the carrier in the solder paste, and reflowing the solder by vapor phase reflow process. The carriers can be pretined and then placed in screened on solder paste on the substrate and the solder reflowed.
In general, prior art techniques for mounting leadless chip carriers have been found inadequate. The solder connection at the carrier perimeter is the primary thermal conduction path from the IC chip to the mounting substrate since the carrier is spaced above the substrate by the height of the solder connection. This provides a substantial lateral thermal path from the IC during operation to the substrate, which may have cooling fins on the opposed substrate surface.
It is also difficult to control the amount of solder which forms the electrical connection between the carrier conductor pattern and the printed circuit board conductor pattern. Differing amounts of solder tend to be applied to portions of the carrier, and a limited amount of solder can be applied which results in the leadless carrier being spaced above the substrate by a small distance which is the height of the solder. When there is a mismatch in thermal expansion between the leadless carrier and the substrate, significant stress is generated in the solder joint which can result in fatigue and cracking after numerous thermal cycles.
It is difficult to maintain the leadless carrier in proper alignment with the substrate conductor during vapor phase reflow soldering since the vapor as it condenses on the substrate can float the carrier, permitting its movement from the desired aligned location.